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Lattice Semiconductor
Figure 14. Example Application
CSIX-to-PI40
User Application
CSIX-to-PI40 IP Core User’s Guide
External
CSIX
Interface
CSIX2PI40_
core
Generic
FIFO
Interface
ORSO82G5_
IPC2
Internal
Register
Interface
External
SYSBUS
PowerPC
Interface
The following Verilog ?les for CSIX-to-PI40 core are provided:
? csix2pi40_core.v for the CSIX-to-PI40 IP core
? orso82g5_chip for top-level module that ties all the application components together
Users can use the csix2pi40_core module as a black box in their system designs. Users may also use
orso82g5_chip.v as a template for their own application
Black Box Considerations
Since the core is delivered as a gate-level netlist, the synthesis software will not re-synthesize the internal nets of
the core. For more information regarding Synplify’s black box declaration, please refer to the Instantiating Black
Boxes in Verilog section of the Synplify Reference Manual.
The core implementation consists of synthesis and place and route sections. Each section is described below. Two
synthesis tools, Synplicity ? Synplify ? and LeonardoSpectrum?, are included in Lattice’s ispLEVER software for
seamless processing of designs. The current IP cores are being tested with EDIF ?ow. The following are the step-
by-step procedures for each synthesis tool to generate the EDIF netlist containing the IP core as a black box.
Synthesis using Synplicity’s Synplify
The step-by-step procedure provided below describes how to run synthesis using Synplify.
1. Launch the Synplify synthesis tool.
2. Select -> Open Project -> Existing Project
navigate to select the following ?le: eval\synthesis\synplicity\user_application\top_001.prj
3. Click on the RUN button. This starts the synthesis process. When complete, the resulting synthesized design
resides in the ?le: TOP.edn.
Synthesis using LeonardoSpectrum
The step-by-step procedure provided below describes how to run synthesis using LeonardoSpectrum.
1. Launch the Leonardo Spectrum synthesis tool.
2. Select -> File -> Run Script
navigate to select the following ?le: eval\synthesis\exemplar\user_application\fpga_syn_001.tcl
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